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COST DRIVER GUIDELINES

General

There are many factors that have cost implications for Printed Wiring Board (PWB) designs. Generally over-engineering and/or over-specifying to the PWB design form or function application can significantly increase the cost. Extremely tight tolerance for lines/spaces, hole sizes, registration and controlled impedance etc., may also increase the cost of manufacturing.

Materials

RoHS capable FR4, High Tg, PTFE (Teflon), Polyimide, Low Dk and Low Df type materials are costlier than the Standard FR4 Tg 135 materials. Costs/per sqft between different types of materials can vary widely. Your Mega Circuit representative can help decide which material is best for your design application.

Board/Array Dimensioning

Mega Circuit uses a wide array of panel sizes allowing for optimum material usage. If you have any questions concerning dimensions please contact your Mega Circuit representative.

Layer Counts

Higher layer counts have increased material and processing costs. The following chart can be used as a rough guideline for cost factors as the layer count increases.

Number of Layers Cost Factors
1 Layer X 0.70
2 Layer 1.00 (base line)
4 Layer X 2.00
6 Layer X 3.00
8 Layer X 4.00
10 Layer X 5.00
12 Layer X 6.00
14 Layer X 7.00
16 Layer X 8.00

Hole Sizes/Drilling Aspect Ratio

The higher the number of holes increases drilling processing costs. Smaller hole sizes will reduce the drilling stack height and hit count per drill bit resulting in an increased cost. A typical drilling aspect ratio is roughly 6:1, although higher drilling aspect ratios can be accomplished, they will increase cost significantly. Following is a chart showing the typical increases incurred as the drill size is decreased.

Drilled Hole Size Panel Stack Height Increased Cost Percentage of Drilling
.024" .180" thick (3 .062 pnls) Base Line
.018" .120 thick (2 .062 pnls) 34%
.012" .060" thick (1 .062 pnl) 67%

Line/Space/SMT Pitch Widths

Lines/spaces less than .006 increases processing and handling cost. SMT Pitch less than .020 have the same effect. Copper weights greater than 1 oz increase material cost, etching cost, soldermask cost and require a broader tolerance window with respect to lines/spaces. When manufacturing a PWB the entire part is processed with regard to the tightest design feature.

Example: if design requirements specify one .004 line/space, then the entire manufacturing panel has to be processed as if it had .004 lines/spaces throughout the part.

Surface Finishes/Plating Aspect Ratio

Plating aspect ratio is much different than drilling aspect ratio. A typical plating aspect ratio is approximately 4:1 (i.e. a .015 hole in .062 material thickness). Although higher plating aspect ratios can be accomplished, they increase cost significantly.

Surface finishes that are RoHS compliant affect the cost due to increased processing and cost of materials. All the various surface finishes have advantages and disadvantages with respect to solderability, co-planarity, shelf life and processing implications. Please contact your Mega Circuit representative to discuss in more detail. Following is a list of surface finishes with typical thickness in ascending cost order.

Process Finish Typical Thickness
OSP (Entec) Co-planarity with Cu surface
HASL .0003 min thickness
Immersion White Tin 30-50
Lead-Free HAL .0003 min thickness
Immersion Silver 8-15
ENIG 3-6
Electrolytic Hard Ni/Au Per Spec thickness
Electrolytic Soft Ni/Au Per Spec thickness

Blind/Buried Vias/Mixed Dielectrics

As with any specialty technology, blind/buried via and/or mixed dielectric construction requirements, there are significant cost drivers. These technologies have increased cost implications as a result of multiple set-ups for drilling/lamination/imaging, extensive programming, pattern plating Blind/Buried cores, controlled depth drilling and sequential lamination.

Filled/Plugged Vias

There are cost drivers and application functionality considerations with both filled and plugged vias. The least costly process is covered via pads (no fill or plug). LPI filled via holes have processing implications for both the PCB manufacturer as well as the component assembly process. Non-conductive ceramic plugged vias are approximately twice as costly as a LPI filled via. Conductive Silver plugged vias are approximately two and a half times as costly as a LPI filled via. For both non-conductive ceramic and conductive silver plugged vias the maximum finished hole size that can be plugged is .018 with a maximum aspect ratio of 5:1.

Conclusion

There are many function and cost factors to consider during product design. The above mentioned factors are the most common. If you have any questions, please contact your Mega Circuit representative for more details.

 
 
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